Bit 2—Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for
ICRB.
Bit 2: BUFEB
Description
0
1
ICRD is used for input capture D.
ICRD is used as a buffer register for input capture B.
(Initial value)
Bits 1 and 0—Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for FRC. External clock pulses are counted on the rising edge of
signals input to pin FTCI.
Bit 1: CKS1
Bit 0: CKS0
Description
0
0
1
0
1
øP/2 internal clock source
øP/8 internal clock source
øP/32 internal clock source
External clock source (rising edge)
(Initial value)
1
8.2.7
Timer Output Compare Control Register (TOCR)
Bit
7
—
1
6
—
1
5
—
1
4
OCRS
0
3
2
1
0
OEA
0
OEB
0
OLVLA OLVLB
Initial value
Read/Write
0
0
—
—
—
R/W
R/W
R/W
R/W
R/W
TOCR is an 8-bit readable/writable register that enables output from the output compare pins,
selects the output levels, and switches access between output compare registers A and B.
TOCR is initialized to H'E0 by a reset and in the standby modes.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1.
Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address.
When this address is accessed, the OCRS bit selects which register is accessed. This bit does not
affect the operation of OCRA or OCRB.
Bit 4: OCRS
Description
0
1
OCRA is selected.
OCRB is selected.
(Initial value)
168
HITACHI [ HITACHI SEMICONDUCTOR ]
