Port 3 Data Register (P3DR)
Bit
7
P37
0
6
P36
0
5
P35
0
4
P34
0
3
P33
0
2
P32
0
1
P31
0
0
P30
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3DR is an 8-bit register that stores data for pins P37 to P30. When a P3DDR bit is set to 1, if port
3 is read, the value in P3DR is obtained directly, regardless of the actual pin state. When a P3DDR
bit is cleared to 0, if port 3 is read the pin state is obtained.
P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
Port 3 Input Pull-Up Control Register (P3PCR)
Bit
7
6
5
4
3
2
1
0
P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 3. If
a P3DDR bit is cleared to 0 (designating input) and the corresponding P3PCR bit is set to 1, the
input pull-up transistor is turned on.
P3PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
The input pull-ups cannot be used in slave mode (when the host interface is enabled).
118
HITACHI [ HITACHI SEMICONDUCTOR ]
