7.5.2
Register Configuration and Descriptions
Table 7.8 summarizes the port 4 registers.
Table 7.8 Port 4 Registers
Name
Abbreviation
Read/Write
Initial Value
H'00
Address
H'FFB5
H'FFB7
Port 4 data direction register
Port 4 data register
P4DDR
P4DR
W
R/W
H'00
Port 4 Data Direction Register (P4DDR)
Bit
7
6
5
4
3
2
1
0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P4DDR is an 8-bit register that controls the input/output direction of each pin in port 4. A pin
functions as an output pin if the corresponding P4DDR bit is set to 1, and as an input pin if this bit
is cleared to 0.
P4DDR is a write-only register. Read data is invalid. If read, all bits always read 1.
P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values, so if a transition to software standby mode occurs while a P4DDR bit
is set to 1, the corresponding pin remains in the output state.
If a transition to software standby mode occurs while port 4 is being used by an on-chip
supporting module (for example, for 8-bit timer output), the on-chip supporting module will be
initialized, so the pin will revert to general-purpose input/output, controlled by P4DDR and P4DR.
122
HITACHI [ HITACHI SEMICONDUCTOR ]
