7.4.2
Register Configuration and Descriptions
Table 7.6 summarizes the port 3 registers.
Table 7.6 Port 3 Registers
Name
Abbreviation
Read/Write
W
Initial Value
H'00
Address
H'FFB4
H'FFB6
H'FFAE
Port 3 data direction register
Port 3 data register
P3DDR
P3DR
R/W
H'00
Port 3 input pull-up control
register
P3PCR
R/W
H'00
Port 3 Data Direction Register (P3DDR)
Bit
7
6
5
4
3
2
1
0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P3DDR is an 8-bit register that controls the input/output direction of each pin in port 3. P3DDR is
a write-only register. Read data is invalid. If read, all bits always read 1.
Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded
mode with on-chip ROM enabled), the input/output directions designated by P3DDR are ignored.
Port 3 automatically consists of the input/output pins of the 8-bit data bus (D7 to D0).
The data bus is in the high-impedance state during reset, and during hardware and software
standby.
Mode 3: A pin in port 3 is used for general output if the corresponding P3DDR bit is set to 1, and
for general input if this bit is cleared to 0. P3DDR is initialized to H'00 by a reset and in hardware
standby mode. In software standby mode it retains its existing values, so if a transition to software
standby mode occurs while a P3DDR bit is set to 1, the corresponding pin remains in the output
state.
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HITACHI [ HITACHI SEMICONDUCTOR ]
