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HSD32M32M4V-10 参数 Datasheet PDF下载

HSD32M32M4V-10图片预览
型号: HSD32M32M4V-10
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM模组128Mbyte ( 32M ×32位), 72引脚SIMM基于32Mx8 , 4Banks , 8K参考, 3.3V [Synchronous DRAM Module 128Mbyte ( 32M x 32-Bit ) 72-Pin SIMM based on 32Mx8, 4Banks, 8K Ref., 3.3V]
分类和应用: 动态存储器
文件页数/大小: 10 页 / 83 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit  
HSD32M32M4V  
Auto  
precharge  
precharge  
Read &  
column  
address  
L
Column  
Address  
(A0 ~ A9)  
4
disable  
Auto  
H
H
X
X
L
L
H
H
L
L
H
L
X
X
V
V
H
4,5  
disable  
Column  
Address  
(A0 ~ A9)  
Auto  
precharge  
precharge  
Write &  
column  
address  
L
4
disable  
Auto  
H
4,5  
6
disable  
Burst Stop  
H
H
X
X
L
L
L
L
H
H
L
L
X
X
X
Precharg Bank selection  
V
X
L
X
e
All banks  
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry  
Exit  
H
L
L
H
L
X
X
X
Clock suspend or  
active power down  
X
X
X
H
L
Entry  
H
Precharge power  
down mode  
H
L
Exit  
L
H
H
H
X
X
V
X
DQM  
X
X
X
7
H
L
X
H
X
X
H
No operation command  
H
(V=Valid, X=Don't care, H=Logic high, L=Logic low)  
Notes :  
1. OP Code : Operand code  
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)  
2. MRS can be issued only at all banks precharge state.  
A new command can be issued after 2 CLK cycles of MRS.  
3. Auto refresh functions are as same as CBR refresh of DRAM.  
The automatical precharge without row precharge command is meant by "Auto".  
Auto/self refresh can be issued only at all banks precharge state.  
4. BA0 ~ BA1 : Bank select addresses.  
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.  
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.  
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.  
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.  
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.  
5. During burst read or write with auto precharge, new read/write command can not be issued.  
Another bank read/write command can be issued after the end of burst.  
New row active of the associated bank can be issued at tRP after the end of burst.  
6. Burst stop command is valid at every burst length.  
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),  
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)  
TIMING DIAGRAMS  
Please refer to timing diagram chart (II)  
URL:www.hbe.co.kr  
REV.1.0 (August.2002)  
- 8 -  
HANBit Electronics Co.,Ltd