HANBit
HSD32M32M4V
CKE ³ VIH(min)
CS* ³ VIH(min), tCC=10ns
Input signals are changed
one time during 20ns
CKE ³ VIH(min)
ICC2
N
64
Precharge standby current in
non power-down mode
mA
mA
mA
ICC2NS
CLK £ VIL(max), tCC=¥
Input signals are stable
CKE £ VIL(max), tCC=10ns
CKE&CLK £ VIL(max)
tCC=¥
56
ICC3
P
24
24
Active standby current in
power-down mode
ICC3PS
CKE³ VIH(min),
CS*³ VIH(min), tCC=10ns
Input signals are changed
one time during 20ns
CKE³ VIH(min)
ICC3
N
120
100
Active standby current in
non power-down mode
(One bank active)
ICC3NS
CLK £VIL(max), tCC=¥
Input signals are stable
IO = 0 mA
Operating current
(Burst mode)
Page burst
ICC4
560
840
560
840
460
800
460
800
mA
1
4Banks Activated
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ³ tRC(min)
mA
mA
mA
2
G
F
20
8
Self refresh current
CKE £ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
AC OPERATING TEST CONDITIONS
(vcc = 3.3V ± 0.3V, TA = 0 to 70°C)
PARAMETER
Value
2.4/0.4
1.4
UNIT
AC Input levels (Vih/Vil)
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
URL:www.hbe.co.kr
REV.1.0 (August.2002)
- 5 -
HANBit Electronics Co.,Ltd
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
