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HSD32M32M4V-10 参数 Datasheet PDF下载

HSD32M32M4V-10图片预览
型号: HSD32M32M4V-10
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM模组128Mbyte ( 32M ×32位), 72引脚SIMM基于32Mx8 , 4Banks , 8K参考, 3.3V [Synchronous DRAM Module 128Mbyte ( 32M x 32-Bit ) 72-Pin SIMM based on 32Mx8, 4Banks, 8K Ref., 3.3V]
分类和应用: 动态存储器
文件页数/大小: 10 页 / 83 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit  
HSD32M32M4V  
AC CHARACTERISTICS  
(AC operating conditions unless otherwise noted)  
-A  
MAX MIN  
-8  
-H  
-L  
PARAMETER  
SYMBOL  
UNIT  
NOTE  
MIN  
MAX MIN  
MAX MIN  
MAX  
CLK cycle time CAS  
7.5  
8
-
10  
1000  
10  
12  
latency=3  
tCC  
1000  
1000  
1000  
ns  
ns  
ns  
1
CAS  
-
10  
latency=2  
CAS  
CLK to valid  
output delay  
5.4  
-
6
-
6
6
6
7
latency=3  
CAS  
tSAC  
1,2  
latency=2  
CAS  
Output data  
hold time  
2.7  
-
3
-
3
3
3
3
latency=3  
CAS  
tOH  
2
latency=2  
CLK high pulse width  
CLK low pulse width  
Input setup time  
tCH  
tCL  
2.5  
2.5  
1.5  
0.8  
1
3
3
2
1
1
3
3
2
1
1
3
3
2
1
1
ns  
ns  
ns  
ns  
ns  
3
3
3
3
3
tSS  
tSH  
tSLZ  
Input hold time  
CLK to output in Low-Z  
CLK to output  
in Hi-Z  
CAS  
5.4  
-
6
-
6
6
6
7
ns  
ns  
2
latency=3  
CAS  
tSHZ  
latency=2  
Notes :  
1. Parameters depend on programmed CAS latency.  
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.  
3. Assumed input rise and fall time (tr & tf) = 1ns.  
If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to  
the parameter.  
SIMPLIFIED TRUTH TABLE  
/R  
A
S
/C  
A
S
D
Q
M
CKE  
CKE  
n
/C  
S
/W  
E
BA  
0,1  
A10/  
AP  
A11,A12,  
A9~A0  
n-1  
COMMAND  
NOTE  
Register  
Refresh  
Mode register set  
Auto refresh  
H
H
X
H
L
L
L
L
L
L
X
OP code  
X
1,2  
3
L
L
H
X
Entry  
3
Self  
refres  
h
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit  
L
H
X
X
X
X
3
Bank active & row addr.  
H
V
Row address  
HANBit Electronics Co.,Ltd  
URL:www.hbe.co.kr  
REV.1.0 (August.2002)  
- 7 -