HANBit
HDD128M72D18RPW
SIMPLIFIED TRUTH TABLE
/R
A
S
L
/C
A
S
L
CKE
CKE
n
BA
0,1
A10/
AP
A11,A12
A9~A0
COMMAND
/CS
/WE
DM
NOTE
n-1
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
X
X
OP code
1,2
1,2
3
Mode register set
Auto refresh
Entry
L
L
OP code
H
L
L
L
H
X
X
3
Refresh
Self
L
H
L
H
X
L
H
X
H
H
X
H
3
refresh
Exit
L
H
X
X
X
X
3
Bank active & row addr.
H
V
V
Row address
Read &
Auto precharge disable
Auto precharge eable
Auto precharge disable
Auto precharge enable
L
H
L
4
4
Column
Address
H
H
X
X
L
L
H
H
L
L
H
X
X
column
address
Write &
column
address
H
L
L
L
4
Column
Address
V
H
4,6
7
Burst Stop
Bank selection
All banks
H
H
X
X
L
L
H
L
H
H
X
X
X
V
X
L
Precharge
X
H
5
H
L
X
V
X
X
H
X
V
X
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock suspend or
active power down
X
X
X
H
L
Entry
H
Precharge power
down mode
H
L
Exit
L
H
H
H
X
X
V
X
DM
X
X
8
H
L
X
X
X
H
No operation command
H
H
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0)
URL : www.hbe.co.kr
12
HANBit Electronics Co.,Ltd.
REV 1.0 (January. 2005)
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
