Preliminary
GS84018/32/36AT/B-180/166/150/100
Pipelined SCD Read Cycle Timing
Single Read
Burst Read
CK
tKL
tKH
tH
tH
tS
tKC
ADSP is blocked by E1 inactive
ADSP
ADSC
tS
ADSC initiated read
Suspend Burst
tS
tH
ADV
tH
tS
RD2
RD3
tH
RD1
A0–A17
GW
tS
tS
tH
BW
BWA–BWD
E1
tH
tH
tH
tS
E1 masks ADSP
tS
tS
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
E3
tOE
G
tOHZ
tKQX
tKQX
tOLZ
tLZ
Hi-Z
DQA–DQD
Q1a
Q2a
Q2b
Q2d
Q3a
Q2c
tHZ
tKQ
Rev: 1.12 7/2002
23/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com