Preliminary
GS84018/32/36AT/B-180/166/150/100
Flow Through Read-Write Cycle Timing
Single Write
Burst Read
Single Read
CK
tS tH
tKC
ADSP is blocked by E inactive
ADSC initiated read
tKH tKL
ADSP
ADSC
tS tH
tS tH
ADV
tS
tH
RD2
WR1
RD1
A0–An
tS
tS
tH
GW
tH
BW
tS
tH
BA–BD
WR1
tS
tS
tS
tH
E1 masks ADSP
E1
tH
tH
E2 and E3 only sampled with ADSP and ADSC
E2
E3
Deselected with E3
tOHZ
Q1a
tOE
G
tS
tH
tKQ
Hi-Z
DQA–DQD
D1a
Q2a
Burst wrap around to it’s initial state
Q2a
Q2b
Q2c
Q2d
Rev: 1.12 7/2002
22/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com