Preliminary
GS84018/32/36AT/B-180/166/150/100
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tS
tKH
tS
tH
ADSP is blocked by E1 inactive
tKC
ADSP
ADSC
ADV
tH
ADSC initiated read
tH
tS
Suspend Burst
Suspend Burst
tS
tH
RD1
RD2
RD3
A0–An
GW
tS
tS
tH
tH
BW
BA–BD
E1
tH
tH
tH
tS
E1 masks ADSP
tS
tS
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
E3
G
tOHZ
tOE
tKQX
tKQX
tOLZ
Q2b
Q2c
Q3a
Q1a
Q2a
Q2d
DQA–DQD
Hi-Z
tLZ
tHZ
tKQ
Rev: 1.12 7/2002
21/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com