Preliminary
GS84018/32/36AT/B-180/166/150/100
AC Test Conditions
Parameter
Conditions
Input high level
Input low level
2.3 V
0.2 V
Input slew rate
1 V/ns
1.25 V
1.25 V
Fig. 1& 2
Input reference level
Output reference level
Output load
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t , t , t and t
.
OHZ
LZ HZ OLZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225Ω
225Ω
DQ
*
50Ω
VT = 1.25 V
30pF
*
5pF
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1uA
IL
V
≥ V ≥ V
–1 uA
1 uA
DD
IN
IH
IH
I
ZZ Input Current
INZZ
0V ≤ V ≤ V
–1 uA 300 uA
IN
V
≥ V ≥ V
–300 uA 1 uA
DD
IN
IL
IL
I
Mode Pin Input Current
Output Leakage Current
INM
0V ≤ V ≤ V
–1uA
1 uA
1 uA
IN
Output Disable,
V
I
–1 uA
OL
= 0 to V
OUT
DD
V
I
I
= –4 mA, V
= –4 mA, V
= 2.375 V
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
OH
OH
OH
DDQ
DDQ
V
= 3.135 V
OH
V
I
= 4 mA
OL
0.4 V
OL
Rev: 1.12 7/2002
17/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
GSI [ GSI TECHNOLOGY ]
