GS74116ATP/J/X
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
7, 8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
256K x 16
4Mb Asynchronous SRAM
Features
SOJ 256K x 16-Pin Configuration (Package J)
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 150/130/105/95 mA at
minimum cycle time
A4
A3
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A6
2
• Single 3.3 V power supply
A2
A7
3
• All inputs and outputs are TTL-compatible
• Byte control
A1
OE
4
Top view
A0
UB
5
• Fully static operation
CE
LB
6
• Industrial Temperature Option: –40° to 85°C
• Package line up
DQ1
DQ2
DQ3
DQ4
VDD
DQ16
DQ15
DQ14
7
8
J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
X: 6 mm x 10 mm Fine Pitch Ball Grid Array
package
9
10
11
12
13
14
15
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
44-pin
SOJ
VSS
DQ5
DQ6
DQ7
DQ8
WE
Description
16
17
18
The GS74116A is a high speed CMOS Static RAM organized
as 262,144 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS74116A is available in a 6 x 10 mm Fine
Pitch BGA package, 400 mil SOJ and 400 mil TSOP Type-II
packages.
A15
A14
A13
A12
A16
A8
A9
19
20
21
22
A10
A11
A17
FP-BGA 256K x 16 Bump Configuration (Package X)
Pin Descriptions
1
2
3
4
5
6
Symbol
A0–A17
Description
Address input
DQ1–DQ16
CE
Data input/output
Chip enable input
A
B
C
D
E
F
LB
OE
A0
A3
A1
A4
A6
A7
A2
NC
DQ16 UB
CE DQ1
DQ2 DQ3
DQ4 VDD
Lower byte enable input
(DQ1 to DQ8)
LB
DQ14 DQ15 A5
VSS DQ13 A17
VDD DQ12 NC
DQ11 DQ10 A8
Upper byte enable input
(DQ9 to DQ16)
UB
A16 DQ5 VSS
WE
OE
Write enable input
Output enable input
+3.3 V power supply
A9
DQ7 DQ6
WE DQ8
V
DD
G
H
DQ9 NC
NC A12
A10
A13
A11
A14
V
Ground
SS
A15
NC
NC
No connect
6 x 10 mm Bump Pitch
© 2001, Giga Semiconductor, Inc.
Rev: 1.03 10/2002
1/14
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
