GS74108ATP/J/X
AC Test Conditions
Output Load 1
Parameter
Input high level
Input low level
Conditions
VIH = 2.4 V
VIL = 0.4 V
tr = 1 V/ns
tf = 1 V/ns
1.4 V
DQ
1
30pF
50Ω
Input rise time
VT = 1.4 V
Input fall time
Input reference level
Output reference level
Output load
Output Load 2
1.4 V
3.3 V
Fig. 1& 2
589Ω
434Ω
DQ
Notes:
1
1. Include scope and jig capacitance.
5pF
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
AC Characteristics
Read Cycle
-8
-10
-12
Parameter
Symbol
Unit
Min
8
Max
—
8
Min
Max
—
Min
12
—
—
—
3
Max
—
Read cycle time
tRC
tAA
tAC
tOE
tOH
10
—
—
—
3
ns
ns
ns
ns
ns
ns
Address access time
—
—
—
3
10
10
4
12
12
5
Chip enable access time (CE)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
8
3.5
—
—
—
—
*
3
3
—
3
—
tLZ
*
Output enable to output in low Z (OE)
Chip disable to output in High Z (CE)
0
—
4
0
—
5
0
—
6
ns
ns
ns
tOLZ
*
—
—
—
—
—
—
tHZ
*
Output disable to output in High Z (OE)
3.5
4
5
tOHZ
* These parameters are sampled and are not 100% tested.
Rev: 1.07 1/2006
5/13
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
