GS4576C09/18/36L
AC Electrical Characteristics
–18
–24
–25
–33
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Clock
Input Clock Cycle Time
Input data clock cycle time
Clock jitter: period
tCK
tDK
1.875
5.7
2.5
5.7
2.5
5.7
3.3
5.7
ns
ns
ps
—
—
tCK
tCK
tCK
tCK
tJITPER
–100
—
100
200
–150
—
150
300
–150
—
150
300
–200
—
200
400
5, 6
tJITCC
Clock jitter: cycle-to-cycle
Clock High Time
ps
—
—
tCKH
tDKH
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCKL
tDKL
Clock Low Time
tCK
—
Clock to input data clock
tCKDK
tMRSC
–0.3
6
0.3
—
–0.45
6
0.5
—
–0.45
6
0.5
—
–0.45
6
1.2
—
ns
—
—
Mode register set cycle time
to any command
tCK
Setup Times
Address/command and input
setup time
tAS/tCS
tDS
0.3
—
—
0.4
—
—
0.4
—
—
0.5
0.3
—
—
ns
ns
—
—
Data–in and data mask to
DK set up time
0.17
0.25
0.25
Hold Times
Address/command and input
hold time
Data-in and data mask to
DK setup time
tAH/tCS
tDH
0.3
—
—
0.4
—
—
0.4
—
—
0.5
0.3
—
—
ns
ns
—
—
0.17
0.25
0.25
Data and Data Strobe
tCKH
tCKL
Output data clock High time
tQKH
tQKL
0.9
0.9
1.1
1.1
0.9
0.9
1.1
1.1
0.9
0.9
1.1
1.1
0.9
0.9
1.1
1.1
—
—
Output data clock Low time
Half–clock period
MIN
(tQKH, tQKL)
MIN
(tQKH, tQKL)
MIN
(tQKH, tQKL)
MIN
(tQKH, tQKL)
tQHP
—
0.2
—
0.25
0.2
—
0.25
0.2
—
0.3
—
ns
ns
—
—
7
QK edge to clock edge skew
tCKQK
–0.2
–0.25
–0.25
–0.3
tQKQ0,
tQKQ1
QK edge to output data
edge
–0.12
–0.22
0.12
–0.2
–0.3
–0.2
–0.3
–0.25
–0.35
0.25
QK edge to any output data
edge
tQKQ
0.22
0.3
0.3
0.35
ns
8
QK edge to QVLD
Data Valid Window
tQKVLD
tDVW
–0.22
0.22
—
–0.3
0.3
—
–0.3
0.3
—
–0.35
0.35
—
ns
—
—
9
tDVW (MIN)
tDVW (MIN)
tDVW (MIN)
tDVW (MIN)
Rev: 1.04 11/2013
47/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
