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GS4576C18GL-33T 参数 Datasheet PDF下载

GS4576C18GL-33T图片预览
型号: GS4576C18GL-33T
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用:
文件页数/大小: 62 页 / 2381 K
品牌: GSI [ GSI TECHNOLOGY ]
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GS4576C09/18/36L  
Capacitance  
Description  
Symbol  
Conditions  
Min.  
1.0  
3.0  
1.5  
1.5  
Max.  
2.0  
Unit  
pF  
C
Address/control input capacitance  
Input/Output capacitance (DQ, DM, and QK, QK)  
Clock capacitance (CK/CK and DK/DK)  
JTAG pins  
I
C
4.5  
pF  
O
TA = 25° C; f = 100 MHz  
V
= V  
= 1.8 V  
DD  
DDQ  
C
2.5  
pF  
CK  
C
4.5  
pF  
JTAG  
Notes:  
1. Capacitance is not tested on the ZQ pin.  
2. JTAG Pins are tested at 50 MHz.  
IDD Operating Conditions  
Description  
Condition  
Symbol  
-18  
-24  
-25  
-33  
I
1 (V ) x9/x18  
55  
55  
55  
55  
55  
55  
5
55  
55  
SB  
DD  
tCK = idle, All banks idle; No inputs  
toggling.  
I
1 (V ) x36  
Standby Current  
mA  
mA  
SB  
DD  
I
1 (V  
)
EXT  
5
5
5
SB  
I
I
2 (V ) x9/x18  
385  
385  
5
360  
360  
5
360  
360  
5
340  
340  
5
SB  
DD  
CS = 1, No commands; Bank address  
incremented and half address/data change  
once every four clock cycles.  
I
2 (V ) x36  
Active Standby Current  
SB  
DD  
I
2 (V  
)
EXT  
SB  
BL = 2, Sequential bank access; Bank  
transitions once every tRC; Half address  
transitions once every tRC; Read followed  
by Write sequence; Continuous data during  
Write Commands.  
1 (V ) x9/x18  
495  
510  
470  
485  
445  
455  
425  
435  
DD  
DD  
I
1 (V ) x36  
DD  
DD  
Operational Current  
Operational Current  
mA  
mA  
I
1 (V  
)
EXT  
15  
15  
15  
10  
DD  
BL = 4, Sequential bank access; Bank  
I
I
2 (V ) x9/x18  
495  
540  
480  
525  
450  
485  
435  
470  
DD  
DD  
transitions once every t ; Half address  
RC  
I
2 (V ) x36  
DD  
DD  
transitions once every t ; Read followed  
RC  
by Write sequence; Continuous data during  
Write Commands.  
I
2 (V  
)
EXT  
25  
25  
25  
20  
DD  
BL = 8, Sequential bank access; Bank  
3 (V ) x9/x18  
580  
665  
555  
640  
500  
570  
480  
550  
DD  
DD  
transitions once every t ; Half address  
RC  
I
3 (V ) x36  
DD  
DD  
Operational Current  
transitions once every t . Read followed  
mA  
mA  
RC  
by Write sequence; Continuous data during  
Write Commands.  
I
3 (V  
)
EXT  
40  
40  
40  
30  
DD  
I
1 (V ) x9/x18  
720  
720  
60  
625  
625  
60  
615  
615  
60  
540  
540  
45  
REF  
DD  
Eight bank cyclic refresh; Continuous  
address/data; Command bus remains in  
refresh for all eight banks.  
I
1 (V ) x36  
Burst Refresh Current  
REF  
DD  
I
1 (V  
)
EXT  
REF  
Rev: 1.04 11/2013  
45/62  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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