GS4576C09/18/36L
IDD Operating Conditions (Continued)
Description
Condition
Symbol
-18
-24
-25
-33
I
2 (V )x9/x18
425
425
15
400
400
15
390
390
15
370
370
10
REF
DD
Single bank refresh; Sequential bank
Distributed Refresh Current access; Half address transitions once every
tRC; Continuous data.
I
2 (V )x36
mA
mA
mA
mA
mA
mA
mA
REF
DD
I
2 (V
)
EXT
REF
I
2W (V ) x9/x18
BL= 2; Cyclic bank access; Half of address
Operating Burst Write Current bits change every clock cycle; Continuous
960
995
60
820
855
60
810
850
60
695
735
45
DD
DD
I
2W (V ) x36
DD
DD
Example
data; Measurement is taken during
continuous Write.
I
2W (V
)
EXT
DD
I
4W (V )x9/x18
BL= 4; Cyclic bank access; Half of address
bits change every two clock cycles;
Continuous data; Measurement is taken
during continuous Write.
755
895
55
655
765
55
655
765
55
575
660
40
DD
DD
Operating Burst Write Current
Example
I
4W (V ) x36
DD
DD
I
4W (V
)
EXT
DD
I
8W (V ) x9/x18
BL= 8; Cyclic bank access; Half of address
bits change every four clock cycles;
Continuous data; Measurement is taken
during continuous Write.
720
855
55
620
730
55
620
730
55
540
630
40
DD
DD
Operating Burst Write Current
Example
I
8W (V ) x36
DD
DD
I
8W (V
)
EXT
DD
BL= 2; Cyclic bank access; Half of address
bits change every clock cycle; Continuous
data; Measurement is taken during
continuous Read.
I
2R (V )x9/x18
850
865
60
725
740
60
720
730
60
620
630
45
DD
DD
Operating Burst Read
Current Example
I
2R (V )x36
DD
DD
I
2R (V
)
EXT
DD
BL= 4; Cyclic bank access; Half of address
bits change every two clock cycles;
Continuous data; Measurement is taken
during continuous Read.
I
I
4R (V ) x9/x18
675
785
55
580
665
55
580
665
55
505
570
40
DD
DD
Operating Burst Read
Current Example
I
4R (V ) x36
DD
DD
I
4R (V
)
EXT
DD
8R (V ) x9/x18
BL= 8; Cyclic bank access; Half of address
bits change every four clock cycles;
Continuous data; Measurement is taken
during continuous Read.
645
760
55
555
645
55
555
645
55
485
550
40
DD
DD
Operating Burst Read
Current Example
I
8R (V ) x36
DD
DD
I
8R (V
)
EXT
DD
Notes:
1. IDD specifications are tested after the device is properly initialized and is operating at worst-case rated temperature and voltage specifications.
2. Definitions of IDD Conditions:
3a. Low is defined as VIN VIL AC
.
(
) MAX
3b. High is defined as VIN VIH AC
.
(
) MIN
3c. Stable is defined as inputs remaining at a High or Low level.
3d. Floating is defined as inputs at VREF = VDDQ/2.
3e. Continuous data is defined as half the DQ signals changng between High and Low every half clock cycle (twice per clock).
3f. Continuous address is defined as half the address signals changing between High and Low every clock cycles (once per clock).
3g. Sequential bank access is defined as the bank address incrementing by one every tRC.
3h. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2 this is every clock, for BL = 4 this
is every other clock, and for BL = 8 this is every fourth clock.
3. CS is High unless a Read, Write, AREF, or MRS command is registered. CS never transitions more than once per clock cycle.
4. IDD parameters are specified with ODT disabled.
5. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operations are tested for the full voltage range specified.
6. IDD tests may use a VIL-to-VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and
parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test
the device is 2 V/ns in the range between VIL AC andVIH AC .
(
)
( )
Rev: 1.04 11/2013
46/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
