GS4576C09/18/36L
IEEE 1149.1 Serial Boundary Scan (JTAG)
LLDRAM II includes an IEEE 1149.1 (JTAG) serial boundary scan Test Access Port (TAP). JTAG ports are generally used to
verify the connectivity of the device once it has been mounted on a Printed Circuit Board (PCB). The port operates in accordance
with IEEE Standard 1149.1-2001 (JTAG). Because the ZQ pin is actually an analog output, to ensure proper boundary-scan testing
of the ZQ pin, Mode Register Bit 8 (M8) needs to be set to 0 until the JTAG testing of the pin is complete. Note that upon power
up, the default state of Mode Register Bit 8 (M8) is Low.
Whenever the JTAG port is used prior to the initialization of the LLDRAM II device, such as when initial conectivity testing is
conducted, it is critical that the CK and CK pins meet V
or that CS be held High from power-up until testing begins. Failure
ID(DC)
to do so can result in inadvertent MRS commands being loaded and causing unexpected test results. Alternately a partial
initialization can be conducted that consists of simply loading a single MRS command with desired MRS Register settings. JTAG
testing may then begin as soon as tMRSC is satisfied. JTAG testing can be conducted after full initilization as well.
The input signals of the test access port (TDI, TMS, and TCK) are referenced to the V as a supply, while the output driver of the
DD
TAP (TDO) is powered by V
.
DDQ
The JTAG test access port incorporates a standardTAP controller from which the Instruction Register, Boundary Scan Register,
Bypass Register, and ID Code Register can be selected. Each of these functions of the TAP controller are described below.
Disabling the JTAG Feature
Use of the JTAG port is never required for RAM operation. To disable the TAP controller, TCK must be tied Low (V ) to prevent
SS
clocking of the device. TDI and TMS are internally pulled up and may be unconnected or they can be connected to V directly or
DD
through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state, which will not
interfere with the operation of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK.
All of the states in the TAP Controller State Diagram are entered through the serial input of the TMS pin. A “0” in the diagram
represents a Low on the TMS pin during the rising edge of TCK while a “1” represents a High on TMS.
Test Data-In (TDI)
The TDI ball is used to serially input test instructions and data into the registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP Controller State Diagram. TDI is connected to the Most Significant Bit
(MSB) of any register (see the TAP Controller Block Diagram).
Test Data-Out (TDO)
The TDO output ball is used to serially clock test instructions and data out from the registers. The TDO output driver is only active
during the Shift-IR and Shift-DR TAP controller states. In all other states, the TDO pin is in a High-Z state. The output changes on
the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register (see the TAP Controller Block
Diagram).
TAP Controller
The TAP controller is a finite state machine that uses the state of the TMS pin at the rising edge of TCK to navigate through its
various modes of operation. See the TAP Controller State Diagram. Each state is described in detail below.
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© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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