3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q80C
7.28. Erase Security Registers (44H)
The GD25Q80C provides four 256-byte Security Registers which can be read and programmed individually. These
registers may be used by the system manufacturers to store security and other important information separately from the
main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low sending Erase Security Registers command
CS# goes high. The command sequence is shown in Figure31. CS# must be driven high after the eighth bit of the command
code has been latched in, otherwise the Erase Security Registers command is not executed. As soon as CS# is driven high,
the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is
in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB) in the Status
Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security Registers will be
permanently locked; the Erase Security Registers command will be ignored.
Address
A23-A16
A15-A10
000000
A9-A0
Security Registers
00000000
Don’t Care
Figure 31. Erase Security Registers command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
44H
24 Bits Address
23 22
MSB
SI
2
1
0
7.29. Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. It allows from 1 to 256 bytes
Security Registers data to be programmed. A Write Enable (WREN) command must previously have been executed to set
the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security Registers
command is entered by driving CS# Low, followed by the command code (42H), three address bytes and at least one data
byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is
initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value of
the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle,
and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
If the Security Registers Lock Bit (LB) is set to 1, the Security Registers will be permanently locked. Program Security
Registers command will be ignored.
Address
A23-A16
00H
A15-A8
00H
A7-A0
Security Registers 0
Security Registers 1
Security Registers 2
Byte Address
Byte Address
Byte Address
00H
01H
00H
02H
34
GILWAY [ GILWAY TECHNICAL LAMP ]
