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GD25Q80CSIG 参数 Datasheet PDF下载

GD25Q80CSIG图片预览
型号: GD25Q80CSIG
PDF下载: 下载PDF文件 查看货源
内容描述: [3.3V Uniform Sector Dual and Quad Serial Flash]
分类和应用:
文件页数/大小: 56 页 / 1271 K
品牌: GILWAY [ GILWAY TECHNICAL LAMP ]
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3.3V Uniform Sector  
Dual and Quad Serial Flash  
GD25Q80C  
7.23. Read Identification (RDID) (9FH)  
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes  
of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the  
device in the second byte. The Read Identification (RDID) command while an Erase or Program cycle is in progress is not  
decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued  
while the device is in Deep Power-Down Mode.  
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. This  
is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being  
shifted out during the falling edge of Serial Clock. The command sequence is shown in Figure 26. The Read Identification  
(RDID) command is terminated by driving CS# to high at any time during data output. When CS# is driven high, the device  
is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and  
execute commands.  
Figure 26. Read Identification ID Sequence Diagram  
CS#  
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15  
SCLK  
SI  
9FH  
Command  
Manufacturer ID  
7
6
5
4
3
2
1
0
SO  
MSB  
CS#  
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31  
SCLK  
SI  
SO  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Memory Type  
JDID15-JDID8  
Capacity  
JDID7-JDID0  
MSB  
MSB  
7.24. High Performance Mode (HPM) (A3H)  
The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when  
operating at high frequencies (see fR and fC1 in AC Electrical Characteristics). This command allows pre-charging of  
internal charge pumps so the voltages required for accessing the flash memory array are readily available. The  
command sequence: CS# goes lowSending A3H commandSending 3-dummy byteCS# goes high. See Figure  
27. After the HPM command is executed, HPF bit of status register will be set to 1, the device will maintain a slightly  
higher standby current (Icc8) than standard SPI operation. The Release from Power-Down or HPM command (ABH) can  
be used to return to standard SPI standby current (Icc1). In addition, Power-Down command (B9H) will also release  
the device from HPM mode back to standard SPI standby state.  
31  
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