3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q80C
Figure 27. High Performance Mode Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
t HPM
Command
A3H
3 Dummy Bytes
23 22
MSB
SI
2
1
0
SO
High Performance Mode
7.25. Continuous Read Mode Reset (CRMR) (FFH)
The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further reduce
command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not require the
BBH/EBH/E7H command code.
Because the GD25Q80C has no hardware reset pin, so if Continuous Read Mode bits are set to “AXH”, the GD25Q80C
will not recognize any standard SPI commands. So Continuous Read Mode Reset command will release the Continuous
Read Mode from the “AXH” state and allow standard SPI command to be recognized. The command sequence is show in
Figure28.
Figure 28. Continuous Read Mode Reset Sequence Diagram
Mode Bit Reset for Quad/Dual I/O
CS#
0
1
2
3
4
5
6
7
SCLK
SI(IO0)
FFH
SO(IO1)
Don`t Care
Don`t Care
Don`t Care
WP#(IO2)
HOLD#(IO3)
32
GILWAY [ GILWAY TECHNICAL LAMP ]
