GS9090 Data Sheet
3. Detailed Description
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Functional Overview on page 20
Serial Digital Input on page 21
Clock and Data Recovery on page 21
Serial-To-Parallel Conversion on page 21
Modes Of Operation on page 22
SMPTE Functionality on page 25
DVB-ASI Functionality on page 29
Data-Through functionality on page 29
Additional Processing Features on page 30
Internal FIFO Operation on page 46
Parallel Data Outputs on page 55
Programmable Multi-Function Outputs on page 56
GS9090 Low-latency Mode on page 58
GSPI Host Interface on page 59
JTAG Operation on page 63
Device Power Up on page 64
3.1 Functional Overview
The GS9090 is a 270Mb/s reclocking deserializer with an internal FIFO and
programmable multi-function output port. The device has two basic modes of
operation which determine precisely how SMPTE or DVB-ASI compliant input data
streams are reclocked and processed.
In Auto mode (AUTO/MAN = HIGH), the GS9090 will automatically detect, reclock,
deserialize, and process SD SMPTE 259M-C, or DVB-ASI input data.
In Manual mode (AUTO/MAN = LOW), the application layer must set external
device pins for the correct reception of either SMPTE or DVB-ASI data. Manual
mode also supports the reclocking and deserializing of 270Mb/s data not
conforming to SMPTE or DVB-ASI streams.
The digital signal processing core implements several data processing functions
including error detection and correction and automatic video standards detection.
These features are all enabled by default, but may be individually disabled via
internal registers accessible through the GSPI host interface.
The provided programmable multi-function output pins may be configured to output
various status signals including H, V, and F timing, ancillary data detection, EDH
detection, and a FIFO load pulse. The internal FIFO supports 4 modes of
operation, which may be used for data alignment / delay, MPEG packet extraction,
or ancillary data extraction.
The GS9090 contains a JTAG interface for boundary scan test implementations.
28201 - 1 July 2005
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