GS9090 Data Sheet
3.2 Serial Digital Input
The GS9090 contains a current mode differential serial digital input buffer, allowing
the device to be connected to SMPTE 259M-C compliant serial digital input signals.
The input buffer has internal 50Ω termination resistors, which are connected to
ground via the TERM pin. If the input signal is AC coupled to the device, the signal
source common mode level will be set internally to approximately 1.45V.
3.3 Clock and Data Recovery
The output of the serial digital input buffer passes to the GS9090's internal
reclocker block. The function of this block is to lock to the input data stream, extract
a clean clock, and retime the serial digital data to remove high frequency jitter.
The operating centre frequency of the internal reclocker is 270Mb/s where the input
jitter tolerance (IJT) is +/- 0.2UI at this rate.
If the reclocker locks to the signal, it will provide internal pll_lock and carrier_detect
signals to the lock detect block of the device.
3.3.1 Internal VCO and Phase Detector
The GS9090 uses an internal VCO and PFD as part of the internal reclocker's
phase-locked loop. Each block requires a +1.8V DC power supply, which is
supplied via the VCO_VDD / VCO_GND and PLL_VDD / PLL_GND pins.
3.4 Serial-To-Parallel Conversion
The retimed data and phase-locked clock signals from the internal reclocker are
fed to the serial-to-parallel converter. The function of this block is to extract 10-bit
parallel data words from the reclocked serial data stream and simultaneously
present them to the SMPTE and DVB-ASI word alignment blocks.
28201 - 1 July 2005
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