GS9090 Data Sheet
Power Up
or RESET
Device
sets LOCKED
pin LOW
(Input data invalid)
NO
Valid Serial
Digital Input?
YES
Device
Device
outputs 27MHz +/- 7.5%
clock on PCLK pin
NO
YES
sets SMPTE_BYPASS
and DVB_ASI pins LOW
Internal reclocker
locked?
Device in Auto Mode?
NO
YES
(Device in
Manual Mode)
Device
sets all other
output pins LOW
SMPTE TRS or
DVB-ASI sync words
detected?
NO
YES
Application layer must set SMPTE_BYPASS
and DVB_ASI pins to support different
functionalities.
Device sets
LOCKED pin HIGH
Device sets SMPTE_BYPASS
and DVB_ASI status pins
(Section 3.5.2)
Device outputs accurate
27MHz clock on PCLK pin
Figure 3-2: Lock Detection Process
The lock detection algorithm first determines if a valid serial digital input signal has
been presented to the device by sampling the internal carrier_detect signal. When
the serial data input is considered invalid the LOCKED pin will be set LOW, and all
device outputs will be forced LOW, except PCLK. The PCLK output frequency will
o
o
be 27MHz +/- 7.5% over the temperature range of -20 C to +85 C.
If a valid serial digital input signal has been detected, and the device is in Auto
mode, the lock algorithm will attempt to detect the presence of either SMPTE TRS
words or DVB-ASI sync words. Assuming that a valid 270Mb/s SMPTE or DVB-ASI
signal has been applied to the device, the LOCKED pin will be set HIGH and the
synchronous and asynchronous lock times will be as listed in the AC Electrical
Characteristics table.
In Manual mode, the application layer must set the SMPTE_BYPASS and
DVB_ASI pins appropriately so that the lock detect block will search for either
SMPTE TRS or DVB-ASI sync words. Synchronous and asynchronous lock times
are also listed in the AC Electrical Characteristics table.
28201 - 1 July 2005
23 of 70
GENNUM [ GENNUM CORPORATION ]
