GS9090 Data Sheet
NOTE: The PCLK output will continue to operate at 27MHz +/- 7.5% during the lock
detection process. Only when the device is locked (LOCKED = HIGH) will the
PCLK output an accurate 27MHz signal.
For SMPTE and DVB-ASI inputs, the lock detect block will only assert the LOCKED
output pin HIGH if (1) the reclocker has locked to the input data stream, and (2)
TRS or DVB-ASI sync words have been correctly identified.
For serial inputs that do not conform to SMPTE or DVB-ASI formats, one of the
following will occur once the reclocker has locked:
1. In Manual mode, data will be passed directly to the parallel outputs without any
further processing taking place and the LOCKED signal will be asserted HIGH
if and only if the SMPTE_BYPASS and DVB_ASI input pins are set LOW (see
Data-Through functionality on page 29); or
2. In Auto mode, the LOCKED signal will be asserted LOW, the parallel outputs
will be set to logic LOW, and the SMPTE_BYPASS and DVB_ASI output
signals will also be set LOW.
If the internal reclocker does not lock to the input, the internal pll_lock signal will be
LOW, and the lock detect block will not search for sync words. The LOCKED signal
will be set LOW, and all device outputs except PCLK will be forced LOW. The
PCLK output frequency will be 27MHz +/- 7.5% over the temperature range of
o
o
-20 C to +85 C.
3.5.2 Auto Mode
Recall that the GS9090 is in Auto mode when the AUTO/MAN input pin is set HIGH
by the application layer. In this mode, SMPTE_BYPASS and DVB_ASI become
output status pins. Table 3-1 shows the status of these pins when different serial
digital video signals are applied.
Table 3-1: Auto Mode Output Status Signals
Pin Settings
Format
SMPTE_BYPASS
DVB_ASI
SD SMPTE
HIGH
LOW
LOW
LOW
HIGH
LOW
DVB-ASI
NOT SMPTE OR DVB-ASI*
*NOTE: In this case the device will not be locked (LOCKED = LOW), and all digital output pins
except PCLK will be set LOW (see Lock Detect on page 22)
28201 - 1 July 2005
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GENNUM [ GENNUM CORPORATION ]
