GS9060 Data Sheet
3.14 Device Power Up
Because the GS9060 is designed to operate in a multi-volt environment, any power
up sequence is allowed. The charge pump, phase detector, core logic, serial digital
input/output buffers and digital I/O buffers should all be powered up within 1ms of
one another.
Device pins may also be driven prior to power up without causing damage.
To ensure that all internal registers are cleared upon power-up, the application
layer must hold the RESET_TRST signal LOW for a minimum of 1ms after the core
power supply has reached the minimum level specified in the DC Electrical
Characteristics Table Table 2-1. See Figure 3-15.
3.15 Device Reset
In order to initialize all internal operating conditions to their default states the
application layer must hold the RESET_TRST signal LOW for a minimum of t
= 1ms.
reset
When held in reset, all device outputs will be driven to a high-impedance state.
+1.8V
+1.65V
CORE_VDD
treset
treset
RESET_TRST
Reset
Reset
Figure 3-15: Reset Pulse
22208 - 8 January 2007
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