GS9060 Data Sheet
3.13 JTAG
When the JTAG/HOST input pin of the GS9060 is set HIGH, the host interface port
will be configured for JTAG test operation. In this mode, pins 27 through 30
become TMS, TDO, TDI, and TCK. In addition, the RESET_TRST pin will operate
as the test reset pin.
Boundary scan testing using the JTAG interface will be enabled in this mode.
There are two methods in which JTAG can be used on the GS9060:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly; or
2. Under control of the host for applications such as system power on self tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other
devices driving the digital I/O pins. If the tests are to be applied only at ATE, this
can be accomplished with tri-state buffers used in conjunction with the
JTAG/HOST input signal. This is shown in Figure 3-13.
Application HOST
GS9060
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
In-circuit ATE probe
Figure 3-13: In-Circuit JTAG
Alternatively, if the test capabilities are to be used in the system, the host may still
control the JTAG/HOST input signal, but some means for tri-stating the host must
exist in order to use the interface at ATE. This is represented in Figure 3-14.
Application HOST
GS9060
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
Tri-State
In-circuit ATE probe
Figure 3-14: System JTAG
Please contact your Gennum representative to obtain the BSDL model for the
GS9060.
22208 - 8 January 2007
54 of 61
GENNUM [ GENNUM CORPORATION ]
