GS9060 Data Sheet
3.5 Serial-To-Parallel Conversion
The retimed data and phase-locked clock signals from the reclocker are fed to the
serial-to-parallel converter. The function of this block is to extract 10-bit data words
from the reclocked serial data stream and present them to the SMPTE and
DVB-ASI word alignment blocks simultaneously.
3.6 Lock Detect
The lock detect block controls the centre frequency of the integrated reclocker to
ensure lock to the received serial digital data stream is achieved, and indicates via
the LOCKED output pin that the device has detected the appropriate sync words.
In Data Through mode, the detection for appropriate sync words is turned off. The
LOCKED pin is an indication of analog lock.
Lock detection is a continuous process, which begins at device power up or after
a system reset, and continues until the device is powered down or held in reset.
The lock detection algorithm first determines if a valid serial digital input signal has
been presented to the device by sampling the internal carrier_detect signal. As
described in Section 3.2.2 on page 25, this signal will be LOW when a good serial
digital input signal has been detected.
If the carrier_detect signal is HIGH, the serial data into the device is considered
invalid, and the VCO frequency will be set to the centre of the pull range. The
LOCKED pin will be LOW and all outputs of the device except for the PCLK output
will be muted. Instead, the PCLK output frequency will operate within +/-3% of the
rates shown in Table 3-15 of Section 3.11.5 on page 51.
NOTE: When the device is operating in DVB-ASI mode, the parallel outputs will not
mute when the carrier_detect signal is HIGH. The LOCKED signal will function
normally.
If a valid input signal has been detected the lock algorithm will enter a hunt phase
where four attempts are made to detect the presence of either SMPTE TRS sync
words or DVB-ASI sync words. The centre frequency of the reclocker will be
270Mb/s.
Assuming that a valid SMPTE or DVB-ASI signal has been applied to the device,
asynchronous lock times will be as listed in AC Characteristics, Table 2-2.
NOTE: The PCLK output will continue to operate during the lock detection process.
The frequency may toggle will be 27MHz when the 20bit/10bit pin is set LOW, and
13.5MHz when 20bit/10bit is set HIGH.
For SMPTE and DVB-ASI inputs, the lock detect block will only assert the LOCKED
output signal HIGH if (1) the reclocker has locked to the input data stream as
indicated by the internal pll_lock signal, and (2) TRS or DVB-ASI sync words have
been correctly identified.
22208 - 8 January 2007
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