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GS9060-CF 参数 Datasheet PDF下载

GS9060-CF图片预览
型号: GS9060-CF
PDF下载: 下载PDF文件 查看货源
内容描述: HD - LINX II SD- SDI和DVB- ASI解串器,带环通电缆驱动器 [HD-LINX II SD-SDI and DVB-ASI Deserializer with Loop-Through Cable Driver]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路
文件页数/大小: 61 页 / 885 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS9060 Data Sheet  
3.2.2 Carrier Detect Input  
For each of the differential inputs, an associated carrier detect input signal is  
included, (CD1 and CD2). These signals are generated by Gennum's family of  
automatic cable equalizers.  
When LOW, CDx indicates that a valid serial digital data stream is being delivered  
to the GS9060 by the equalizer. When HIGH, the serial digital input to the device  
should be considered invalid. If no equalizer precedes the device, the application  
layer should set CD1 and CD2 accordingly.  
NOTE: If the GS9064 Automatic Cable Equalizer is used, the MUTE/CD output  
signal from that device must be translated to TTL levels before passing to the  
GS9060 CDx inputs. See Section 4.1 on page 56 for a recommended transistor  
network that will set the correct voltage levels.  
A 2x1 input multiplexer is also provided for these signals. The internal  
carrier_detect signal is determined by the setting of the IP_SEL pin and is used by  
the lock detect block of the GS9060 to determine the lock status of the device,  
Section 3.6 on page 28.  
3.2.3 Single Input Configuration  
If the application requires a single differential input, the second set of inputs may  
be left unconnected. Tie the associated carrier detect pin HIGH, and leave the  
termination pin unconnected.  
3.3 Serial Digital Reclocker  
The output of the 2x1 serial digital input multiplexer passes to the GS9060's  
internal reclocker stage. The function of this block is to lock to the input data  
stream, extract a clean clock, and retime the serial digital data to remove high  
frequency jitter.  
The reclocker was designed with a 'hexabang' phase and frequency detector. That  
is, the PFD used can identify six 'degrees' of phase / frequency misalignment  
between the input data stream and the clock signal provided by the VCO, and  
correspondingly signal the charge pump to produce six different control voltages.  
This results in fast and accurate locking of the PLL to the data stream.  
If lock is achieved, the reclocker provides an internal pll_lock signal to the lock  
detect block of the device.  
22208 - 8 January 2007  
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