GS1560A/GS1561 Data Sheet
3.3 Serial Digital Reclocker
The output of the 2x1 serial digital input multiplexer passes to the
GS1560A/GS1561's internal reclocker stage. The function of this block is to lock to
the input data stream, extract a clean clock, and retime the serial digital data to
remove high frequency jitter.
The reclocker was designed with a 'hexabang' phase and frequency detector. That
is, the PFD used can identify six 'degrees' of phase / frequency misalignment
between the input data stream and the clock signal provided by the VCO, and
correspondingly signal the charge pump to produce six different control voltages.
This results in fast and accurate locking of the PLL to the data stream.
In master mode, the operating center frequency of the reclocker is toggled between
270Mb/s and 1.485Gb/s by the lock detect block, (see Lock Detect on page 35). In
slave mode, however, the center frequency is determined entirely by the SD/HD
input control signal set by the application layer.
If lock is achieved, the reclocker provides an internal pll_lock signal to the lock
detect block of the device.
3.3.1 External VCO
The GS1560A/GS1561 requires the external GO1525 Voltage Controlled
Oscillator as part of the reclocker's phase-locked loop. This external VCO
implementation was chosen to ensure high quality reclocking.
Power for the external VCO is generated entirely by the GS1560A/GS1561 from
an integrated voltage regulator. The internal regulator uses +3.3V DC supplied via
the CP_VDD / CP_GND pins to provide +2.5V DC on the VCO_VCC / VCO_GND
pins.
The control voltage to the VCO is output from the GS1560A/GS1561 on the LF pin
and requires 4.7kΩ pull-up and pull-down resistors to ensure correct operation.
The GO1525 produces a 1.485GHz reference signal for the reclocker, input on the
VCO pin of the GS1560A/GS1561. Both LF and VCO signals should be referenced
to the supplied VCO_GND as shown in the recommended application circuit of
GS1560A Typical Application Circuit (Part A) on page 73.
3.3.2 Loop Bandwidth
The loop bandwidth of the integrated reclocker is nominally 1.4MHz, but may be
increased or decreased via the LB_CONT pin. It is recommended that this pin be
connected to VCO_GND through 39.2kΩ to maximize the input jitter tolerance of
the device.
27360 - 8 September 2005
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GENNUM [ GENNUM CORPORATION ]
