GS1560A/GS1561 Data Sheet
3.5 Serial-To-Parallel Conversion
The retimed data and phase-locked clock signals from the reclocker are fed to the
serial-to-parallel converter. The function of this block is to extract 10-bit or 20-bit
parallel data words from the reclocked serial data stream and present them to the
SMPTE and DVB-ASI word alignment blocks simultaneously.
3.6 Modes Of Operation
The GS1560A/GS1561 has two basic modes of operation which determine how
the lock detect block controls the integrated reclocker. Master mode is enabled
when the application layer sets the MASTER/SLAVE pin HIGH, and slave mode is
enabled when MASTER/SLAVE is set LOW.
3.6.1 Lock Detect
The lock detect block controls the center frequency of the integrated reclocker to
ensure lock to the received serial digital data stream is achieved, and indicates via
the LOCKED output pin that the device has detected the appropriate sync words.
In Data Through mode, the detection for appropriate sync words is turned off. The
LOCKED pin is an indication of analog lock.
Lock detection is a continuous process, which begins at device power up or after
a system reset, and continues until the device is powered down or held in reset.
The lock detection algorithm first determines if a valid serial digital input signal has
been presented to the device by sampling the internal carrier_detect signal. As
described in Carrier Detect Input on page 31, this signal will be LOW when a good
serial digital input signal has been detected.
If the carrier_detect signal is HIGH, the serial data into the device is considered
invalid, and the VCO frequency will be set to the center of the pull range. The
LOCKED pin will be LOW and all outputs of the device except for the PCLK output
will be muted. Instead, the PCLK output frequency will operate within +/-3% of the
rates shown in Table 3-16 of Parallel Output Clock (PCLK) on page 67.
NOTE: When the device is operating in DVB-ASI slave mode only, the parallel
outputs will not mute when the carrier_detect signal is HIGH. The LOCKED signal
will function normally.
If a valid input signal has been detected, and the device is in master mode, the lock
algorithm will enter a hunt phase where four attempts are made to detect the
presence of either SMPTE TRS sync words or DVB-ASI sync words. At each
attempt, the center frequency of the reclocker will be toggled between 270Mb/s and
1.485Gb/s.
Assuming that a valid SMPTE or DVB-ASI signal has been applied to the device,
asynchronous lock times will be as listed in Table 2-2: AC Electrical
Characteristics.
27360 - 8 September 2005
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