MB90610A Series
Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]
Mnemonic
#
~
RG
B
Operation
LH AH
I
S T N
Z
V C RMW
ADD
ADD
ADD
ADD
ADD
ADD
A,#imm8
A, dir
2
2
2
2
5
3
0
0
1
0
2
0
0
1
0
0
0
0
1
0
2
0
0
1
0
0
0
byte (A) ← (A) +imm8
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
(b) byte (A) ← (A) +(dir)
A, ear
0
byte (A) ← (A) +(ear)
(b) byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
A, eam
ear, A
2+ 4+(a)
2
3
0
eam, A
2+ 5+(a)
2× b) byte (eam) ← (eam) + (A)
ADDC
ADDC
ADDC
A
1
2
2
3
0
0
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
A, ear
A, eam
2+ 4+(a)
(b) byte (A) ← (A) + (eam) + (C)
ADDDC A
1
2
2
2
3
2
5
3
0
0
byte (A) ← (AH) + (AL) + (C) (decimal)
byte (A) ← (A) –imm8
SUB
A, #imm8
SUB
A, dir
A, ear
A, eam
ear, A
eam, A
A
(b) byte (A) ← (A) – (dir)
SUB
0
byte (A) ← (A) – (ear)
(b) byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
SUB
2+ 4+(a)
SUB
2
3
0
SUB
2+ 5+(a)
2×(b) byte (eam) ← (eam) – (A)
SUBC
SUBC
SUBC
1
2
2
3
0
0
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
–
–
–
–
A, ear
A, eam
2+ 4+(a)
(b) byte (A) ← (A) – (eam) – (C)
SUBDC A
1
3
0
byte (A) ← (AH) – (AL) – (C) (decimal)
ADDW
A
1
2
2
3
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
0
0
word (A) ← (AH) + (AL)
word (A) ← (A) +(ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
– –
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
ADDW A, ear
ADDW A, eam
2+ 4+(a)
(c) word (A) ← (A) +(eam)
ADDW
A, #imm16
3
2
2
3
0
0
word (A) ← (A) +imm16
word (ear) ← (ear) + (A)
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
2+ 5+(a)
2×(c) word (eam) ← (eam) + (A)
2
3
0
word (A) ← (A) + (ear) + (C)
–
–
–
–
–
–
–
*
2+ 4+(a)
(c) word (A) ← (A) + (eam) + (C)
SUBW
A
1
2
2
3
0
0
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
SUBW A, ear
SUBW A, eam
2+ 4+(a)
(c) word (A) ← (A) – (eam)
SUBW
A, #imm16
3
2
2
3
0
0
word (A) ← (A) –imm16
word (ear) ← (ear) – (A)
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
2+ 5+(a)
2×(c) word (eam) ← (eam) – (A)
2
3
0
word (A) ← (A) – (ear) – (C)
–
–
2+ 4+(a)
(c) word (A) ← (A) – (eam) – (C)
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A, ear
2
6
2
0
0
2
0
0
0
long (A) ← (A) + (ear)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– –
– –
– –
– –
– –
– –
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
A, eam
2+ 7+(a)
(d) long (A) ← (A) + (eam)
A, #imm32
A, ear
5
2
4
6
0
0
long (A) ← (A) +imm32
long (A) ← (A) – (ear)
A, eam
2+ 7+(a)
(d) long (A) ← (A) – (eam)
A, #imm32
5
4
0
long (A) ← (A) –imm32
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
78
FUJITSU [ FUJITSU ]
