MB90610A Series
Table 4 Number of Execution Cycles for Each Type of Addressing
(a)
Number of register
accesses for each type of
addressing
Code
Operand
Number of execution cycles
for each type of addressing
Ri
RWi
RLi
00 to 07
Listed in tables of instructions Listed in tables of instructions
08 to 0B
0C to 0F
10 to 17
18 to 1B
@RWj
2
4
2
2
1
2
1
1
@RWj +
@RWi + disp8
@RWj + disp16
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Note: “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.
Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles
(b) byte
(c) word
(d) long
Number
Number
Number
Operand
Number
of cycles
Number
of cycles
Number
of cycles
of
of
of
access
access
access
Internal register
+0
1
+0
1
+0
2
Internal memory even address
Internal memory odd address
+0
+0
1
1
+0
+2
1
2
+0
+4
2
4
Even address on external data bus (16 bits)
Odd address on external data bus (16 bits)
+1
+1
1
1
+1
+4
1
2
+2
+8
2
4
External data bus (8 bits)
+1
1
+4
2
+8
4
Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value)
in the tables of instructions.
• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
Instruction
Internal memory
Byte boundary
Word boundary
—
—
+3
+2
+3
—
External data bus (16 bits)
External data bus (8 bits)
Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready
input and automatic ready.
• Because instruction execution is not slowed down by all program fetches in actuality, these correction
values should be used for “worst case” calculations.
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