MB90610A Series
Table 14 Logical 2 Instructions (Long Word) [6 Instructions]
Mnemonic
#
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
ANDL A, ear
ANDL A, eam
2
6
2
0
0
long (A) ← (A) and (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 7+ (a)
(d) long (A) ← (A) and (eam)
ORL
ORL
A, ear
A, eam
2
6
2
0
0
long (A) ← (A) or (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 7+ (a)
(d) long (A) ← (A) or (eam)
XORL A, ea
XORL A, eam
2
6
2
0
0
long (A) ← (A) xor (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
2+ 7+ (a)
(d) long (A) ← (A) xor (eam)
Table 15 Sign Inversion Instructions (Byte/Word) [6 Instructions]
Mnemonic
#
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
NEG
A
1
2
0
0
byte (A) ← 0 – (A)
X
–
–
–
–
*
*
*
*
–
NEG
NEG
ear
eam
2
3
2
0
0
byte (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
2+ 5+ (a)
2× (b) byte (eam) ← 0 – (eam)
NEGW
A
1
2
0
0
word (A) ← 0 – (A)
–
–
–
–
–
*
*
*
*
–
NEGW ear
NEGW eam
2
3
2
0
0
word (ear) ← 0 – (ear)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
2+ 5+ (a)
2× (c) word (eam) ← 0 – (eam)
Table 16 Normalize Instruction (Long Word) [1 Instruction]
Mnemonic
#
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
1
NRML A, R0
2
1
0
long (A) ← Shift until first digit is “1”
byte (R0) ← Current shift count
–
–
–
–
–
–
*
–
–
–
*
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
82
FUJITSU [ FUJITSU ]
