MB90610A Series
• State Transition Diagram for Clock Selection
Power-on
Main
Main → PLLX
MCS = 0
MCM = 1
(1)
(2)
(3)
MCS = 1
MCM = 1
CS1/0 = XX
(6)
(7)
CS1/0 = XX
PLL1 → Main
MCS = 1
PLL multiplier = 1
MCS = 0
MCM = 0
CS1/0 = 00
MCM = 0
CS1/0 = 00
(4)
(6)
(7)
(7)
PLL2 → Main
MCS = 1
MCM = 0
PLL multiplier = 2
MCS = 0
MCM = 0
(6)
(5)
CS1/0 = 01
CS1/0 = 01
PLL3 → Main
MCS = 1
MCM = 0
PLL multiplier = 3
MCS = 0
MCM = 0
(7)
(6)
CS1/0 = 10
CS1/0 = 10
PLL4 → Main
MCS = 1
PLL multiplier = 4
MCS = 0
MCM = 0
CS1/0 = 11
MCM = 0
CS1/0 = 11
(6)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
MCS bit cleared
PLL clock oscillation stabilization delay complete and CS1/0 = “00”
PLL clock oscillation stabilization delay complete and CS1/0 = “01”
PLL clock oscillation stabilization delay complete and CS1/0 = “10”
PLL clock oscillation stabilization delay complete and CS1/0 = “11”
MCS bit set (including a hardware standby or watchdog reset)
PLL clock and main clock synchronized timing
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