MB90610A Series
9. Watchdog Timer and Timebase Timer Functions
The watchdog timer consists of a 2-bit watchdog counter, a control register, and a watchdog reset controller.
The watchdog counter uses the carry-up signal from the 18-bit timebase timer as its clock source. In addition
to the 18-bit timer, the timebase timer contains an interval interrupt control circuit. The timebase timer uses the
main clock, regardless of the value of the MCS bit in the CKSCR register.
(1) Register Configuration
bit
7
6
5
4
3
2
1
0
Watchdog timer control register
Address
PONR STBR WRST ERST SRST WTE WT1 WT0
WDTC
TBTC
: 0000A8H
Read/write
Initial value
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(W)
(1)
(W)
(1)
(W)
(1)
bit 15
14
—
13
—
12
11
10
9
8
Timebase timer control register
Address
Reserved
TBIE TBOF TBR TBC1 TBC0
: 0000A9H
Read/write
Initial value
(—) (—) (—) (R/W) (R/W) (W) (R/W) (R/W)
(1)
(—) (—)
(0)
(0)
(1)
(0)
(0)
(2) Block Diagram
Main clock
(OSC oscillator)
TBTC
TBC1
TBC0
TBR
212
Clock input
214
216
219
Timebase timer
Selector
212 214 216 219
TBTRES
S
R
TBIE
TBOF
AND
Q
Timebase
interrupt
WDTC
WT1
Watchdog reset
activation circuit
2-bit counter
OF
WDGRST
To internal reset
activation circuit
Selector
WT0
CLR
CLR
WTE
PONR
STBR
WRST
ERST
SRST
From power-on detection
From hardware standby
control circuit
RST pin
From the RST bit of the
STBYC register
40
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