MB90610A Series
12. External Bus Terminal Control Circuit
This circuit controls the external bus terminals intended to extend outwardly the CPU’s address/data bus.
(1) Register Configuration
bit 15
14
13
12
11
—
10
—
9
8
Register for selection of
AUTO ready function
Address: 0000A5H
IOR1 IOR0 HMR1 HMR0
LMR1 LMR0
ARSR
HACR
ECSR
(W)
(0)
(W)
(0)
(W)
(1)
(W) (—) (—) (W)
(W)
(0)
Read/write
Initial value
(1)
(—) (—)
(0)
bit
7
6
5
4
3
2
1
0
Register for control of
external address output
Address: 0000A6H
E23 E22 E21 E20 E19 E18 E17 E16
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
Read/write
Initial value
bit 15
—
14
13
12
11
10
9
8
Register for selection of
bus control signal
Address: 0000A7H
LMBS WRE HMBS IOBS HDE RYE CKE
(—) (W)
(—) (0)
(W)
(W)
(W)
(W)
(0)
(W)
(0)
(W)
(0)
Read/write
Initial value
(0) (1/0) (0)
(2) Block Diagram
P5
P4
P5
P3
P2
P1
P1 data
P1
P1 direction
RB
Data control
Access control
Access control
Access
control
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