MB90610A Series
10. Low Power Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization
Delay Time, and Clock Multiplier Function)
The following operation modes are available: PLL clock mode, PLL sleep mode, timer mode, main clock mode,
main sleep mode, stop mode, and hardware standby mode. Operation modes other than PLL clock mode are
classified as low power consumption modes.
In main clock mode and main sleep mode, the device operates on the main clock only (OSC oscillator clock).
The PLL clock (VCO oscillator clock) is stopped in these modes and the main clock divided by 2 is used as the
operating clock.
In PLL sleep mode and main sleep mode, the CPU's operating clock only is stopped and other elements continue
to operate.
In timer mode, only the timebase timer operates.
Stop mode and hardware standby mode stop the oscillator. These modes maintain existing data with minimum
power consumption.
TheCPUintermittentoperationfunctionprovidesanintermittentclocktotheCPUwhenregister, internalmemory,
internal resource, or external bus access is performed. This function reduces power consumption by lowering
the CPU execution speed while still providing a high-speed clock to internal resources.
The PLL clock multiplier ratio can be set to 1, 2, 3, 4 by the CS1, 0 bits.
The WS1, 0 bits set the delay time to wait for the main clock oscillation to stabilize when recovering from stop
mode or hardware standby mode.
(1) Register Configuration
bit
7
6
5
4
3
2
1
0
Low power consumption mode
control register
Address: 0000A0H
STP SLP SPL RST Reserved CG1 CG0 Reserved
LPMCR
CKSCR
(W)
(0)
(W) (R/W) (W) (—) (R/W) (R/W) (—)
Read/write
Initial value
(0)
(0)
(1)
(1)
(0)
(0)
(0)
bit 15
14
13
12
11
10
9
8
Clock select register
Reserved MCM WS1 WS0 Reserved MCS CS1 CS0
Address
: 0000A1H
(—)
(1)
(R) (R/W) (R/W) (—) (R/W) (R/W) (R/W)
(1) (1) (1) (1) (1) (0) (0)
Read/write
Initial value
41
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