MB90610A Series
7. DTP/External Interrupts
The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC-16L
CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the
requests to the F2MC-16L CPU to activate the extended intelligent I/O service or interrupt processing. Two
request levels (“H” and “L”) are provided for extended intelligent I/O service. For external interrupt requests,
generation of interrupts on a rising or falling edge as well as on “H”, “L” levels can be selected, giving a total of
four types.
(1) Register Configuration
bit
7
6
5
4
3
2
1
0
Interrupt/DTP enable register
Address
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
ENIR
EIRR
: 000028H
Read/write
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
bit 15
(0)
14
(0)
13
(0)
12
(0)
11
(0)
10
(0)
9
(0)
8
Initial value
Interrupt/DTP register
Address
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
: 000029H
Read/write
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
14
(0)
13
(0)
12
(0)
11
(0)
10
(0)
9
(0)
8
Initial value
bit 15
Request level setting register (upper)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4
Address
: 00002BH
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Read/write
(0)
7
(0)
6
(0)
5
(0)
4
(0)
3
(0)
2
(0)
1
(0)
0
Initial value
bit
Request level setting register (lower)
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
ELVR
Address
: 00002AH
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Read/write
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Initial value
(2) Block Diagram
F2MC-16 bus
8
Interrupt/DTP enable register
Request F/F
Interrupt input
8
8
Gate
Edge detect circuit
Request input
8
8
Interrupt/DTP register
Request level setting register
38
FUJITSU [ FUJITSU ]
