MB90610A Series
2. UART 0/1/2 (SCI)
UART 0/1/2 are serial I/O ports that can be used for CLK asynchronous (start-stop synchronization) or CLK
synchronous (I/O expansion serial) data transfer. The ports have the following features.
• Full duplex, double buffered
• Supports CLK asynchronous (start-stop synchronization) and CLK synchronous (I/O expansion serial) data
transfer
• Multi-processor mode support
• Built-in dedicated baud rate generator
CLK asynchronous: 62500/31250/19230/9615/4808/2404/1202 bps
CLK synchronous: 2 M/1 M/500 K/250 K bps
• Supports flexible baud rate setting using an external clock
• Error detect function (parity, framing, and overrun)
• NRZ type transmission signal
• Intelligent I/O service support
(1) Register Configuration
Serial mode register
: channel 0 000020H
bit
bit
bit
7
6
5
4
3
2
1
0
Address
: channel 1 000024H
: channel 2 000044H
MD1 MD0 CS2 CS1 CS0
–
SCKE SOE
SMR
SCR
(R/W) (R/W) (W)
(W)
(0)
(W)
(0)
(–) (R/W) (R/W)
(–) (0) (0)
Read/write
Initial value
(0)
(0)
(0)
Serial control register
: channel 0 000021H
15
PEN
14
13
SBL
12
11
10
9
8
Address
: channel 1 000025H
: channel 2 000045H
P
CL
A/D REC RXE TXE
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Read/write
Initial value
(0)
(0)
(0)
(0)
(0)
(1)
(0)
(0)
Input data register/
Output data register
7
6
5
4
3
2
1
0
: channel 0 000022H
Address
: channel 1 000026H
: channel 2 000046H
D7
D6
D5
D4
D3
D2
D1
D0
SIDR (read)
SODR (write)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Read/write
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Serial status register
: channel 0 000023H
bit
bit
15
14
13
12
11
10
9
8
Address
: channel 1 000027H
: channel 2 000047H
PE ORE FRE RDRF TDRE
–
RIE
TIE
SSR
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(1)
(–) (R/W) (R/W)
(–) (0) (0)
Read/write
Initial value
Machine clock division
control register
15
14
13
12
11
10
9
8
Address: channel 0 000051H
: channel 1 000053H
: channel 2 000055H
–
–
–
–
DIV3 DIV1 DIV1 DIV0
CDCR
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(W)
(1)
(W)
(1)
(W)
(1)
(W)
(1)
Read/write
Initial value
28
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