MB90610A Series
Note: No register bits are provided for bit 6 to 7 of port 5.
No register bit is provided for bit 7 of port 7.
No register bit is provided for bit 7 of port 8.
No register bits are provided for bits 6 to 7 of port 9.
No register bit is provided for bit 0 of port A.
Port 6 does not have a DDR.
bit
15
14
13
12
11
10
9
8
Analog input enable register
ADER 000016H
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
ADER
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Read/write
Initial value
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2) Register Details
• Port Data Registers
Port data register
bit
15
14
13
12
11
10
9
8
: PDR1 000001H
: PDR3 000003H
: PDR5 000005H
: PDR7 000007H
: PDR9 000009H
Address
PD×7 PD×6 PD×5 PD×4 PD×3 PD×2 PD×1 PD×0
PDR×
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Read/write
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Port data register
: PDR2 000002H
bit
7
6
5
4
3
2
1
0
Address
: PDR4 000004H
: PDR6 000006H
: PDR8 000008H
: PDRA 00000AH
PD×7 PD×6 PD×5 PD×4 PD×3 PD×2 PD×1 PD×0
PDR×
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Read/write
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Note: No register bits are provided for bit 6 to 7 of port 5.
No register bit is provided for bit 7 of port 7.
No register bit is provided for bit 7 of port 8.
No register bits are provided for bits 6 to 7 of port 9.
No register bit is provided for bit 0 of port A.
Port 1 is only available when the external data bus is in 8-bit mode. Access is prohibited in 16-bit mode.
Ports 2, 3 are only available in multiplex mode. Access is prohibited in non-multiplex mode.
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FUJITSU [ FUJITSU ]
