MB90610A Series
• Port Direction Registers
Port direction register
bit
15
14
13
12
11
10
9
8
: DDR1 000011H
: DDR3 000013H
: DDR5 000015H
: DDR7 000017H
: DDR9 000019H
Address
DD×7 DD×6 DD×5 DD×4 DD×3 DD×2 DD×1 DD×0
DDR×
DDR×
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Read/write
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Port direction register
bit
7
6
5
4
3
2
1
0
Address
: DDR2 000012H
: DDR4 000014H
: DDR8 000018H
: DDRA 00001AH
Read/write
DD×7 DD×6 DD×5 DD×4 DD×3 DD×2 DD×1 DD×0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Initial value
When pins are used as ports, the register bits control the corresponding pins as follows.
0: Input mode
1: Output mode
Bits are set to “0” by a reset.
Note: No register bits are provided for bit 6 to 7 of port 5.
No register bit is provided for bit 7 of port 7.
No register bit is provided for bit 7 of port 8.
No register bit is provided for bit 0 of port A.
No register bits are provided for bits 6 to 7 of port 9.
Port 6 does not have a DDR.
Port 1 is only available when the external data bus is in 8-bit mode. Access is prohibited in 16-bit mode.
Ports 2 and 3 are only available in multiplex mode. Access is prohibited in non-multiplex mode.
• Analog Input Enable Register
bit
Analog input enable register
ADER 000016H
15
14
13
12
11
10
9
8
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
ADER
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Read/write
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Initial value
Controls each pin of port 6 as follows.
0: Port input mode
1: Analog input mode
Bits are set to “1” by a reset.
Note: Inputting an intermediate level signal in port input mode causes an input leak current to flow. Therefore, set
to analog input mode when applying an analog input.
25
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