MB90610A Series
3. 10-bit 8-input A/D Converter (With 8-bit Resolution Mode)
The 10-bit 8-input A/D converter converts analog input voltages to digital values. The A/D converter has the
following features.
• Conversion time: Minimum of 6.13 µs per channel (98 machine cycles/16 MHz machine clock. This includes
the sample and hold time)
• Sample and hold time: Minimum of 3.75 µs per channel (60 machine cycles/16 MHz machine clock)
• Uses RC-type successive approximation conversion with a sample and hold circuit.
• 10-bit or 8-bit resolution
• Eight program-selectable analog input channels
Single conversion mode
: Selectively convert a one channel.
Scan conversion mode
: Continuously convert multiple channels. Maximum of 8 program-selectable
channels.
Continuous conversion mode : Repeatedly convert specified channels.
Stop conversion mode : Convert one channel then halt until the next activation. (Enables
synchronization
of the conversion start timing.)
• An A/D conversion completion interrupt request to the CPU can be generated on the completion of A/D
conversion. This interrupt can activate I2OS to transfer the result of A/D conversion to memory and is suitable
for continuous operation.
• Activation by software, external trigger (falling edge), or timer (rising edge) can be selected.
(1) Register Configuration
bit
15
14
13
12
11
10
9
8
A/D control status register (upper)
Address: 00002DH
BUSY INT INTE PAUS STS1 STS0 STRT Reserved
ADCS1
ADCS0
ADCR1
ADCR0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W)
(–)
(0)
Read/write
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
7
6
5
4
3
2
1
0
A/D control status register (lower)
Address: 00002CH
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Read/write
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
15
14
–
13
–
12
–
11
–
10
–
9
8
A/D data register (upper)
Address: 00002EH
S10
D9
D8
(R/W) (R)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(X)
(R)
(X)
Read/write
Initial value
(0)
(0)
bit
7
6
5
4
3
2
1
0
A/D data register (lower)
Address: 00002FH
D7
D6
D5
D4
D3
D2
D1
D0
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
Read/write
Initial value
30
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