MB90560/565 Series
• Block diagram
Internal data bus
TMRLR0*1
TMRLR1*2
16-bit reload register
Reload signal
Reload
control circuit
TMR0*1
TMR1*2
*4
UF
16-bit timer register
CLK
Count clock generation circuit
Clock
pulse
detection
circuit
Gate input
Machine
clock φ
3
Wait signal
Prescaler
To UART0*1
To UART1 and
A/D converter trigger*2
Clear
trigger
Internal
clock
Output control circuit
CLK
Output signal
generation circuit
Input
control
circuit
Pin
Clock
selector
Pin
EN
TO0*1
TO1*2
TIN0*1
TIN1*2
External clock
Select
signal
3
2
Operation
control circuit
Function selection
CSL1 CSL0 MOD2MOD1MOD0OUTE OUTL RELD INTE UF CNTE TRG
Timer control status register (TMCSR)
Interrupt
request output
#30 (1EH) *1, *3
#32 (20H) *2, *3
*1 : Channel 0
*2 : Channel 1
*3 : Interrupt number
*4 : Underflow
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