MB90560/565 Series
• Block diagram
Watchdog timer control register (WDTC)
PONR STBR WRST ERST SRST WTE WT1 WT0
2
Watchdog timer
Start
Reset
Watchdog timer
reset generation
circuit
Change to sleep mode
Counter clear
control circuit
Counter clock
selector
To internal
reset circuit
2-bit counter
Clear
Change to timebase
timer mode
Change to stop mode
4
(Timebase timer/counter)
× 21 × 22 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
Main clock
(HCLK divided into 2)
HCLK : Oscillation clock frequency
35