FEC Electrical Characteristics
Table 35 provides information on the MII and RMII transmit signal timing.
Table 35. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
M6
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid
5
—
4
—
25
—
ns
ns
ns
M20_R RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup
MII
M21_R RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising
2
—
ns
MII
edge
M7
MII_TX_CLK and RMII_REFCLK pulse width high
35%
65%
MII_TX_CLK or
RMII_REFCLK
period
M8
MII_TX_CLK and RMII_REFCLK pulse width low
35%
65%
MII_TX_CLK or
RMII_REFCLK
period
Figure 73 shows the MII transmit signal timing diagram.
M7
MII_TX_CLK (input)
RMII_REFCLK
M5
M8
MII_TXD[3:0] (outputs)
MII_TX_EN
MII_TX_ER
M6
Figure 73. MII Transmit Signal Timing Diagram
15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 36 provides information on the MII async inputs signal timing.
Table 36. MII Async Inputs Signal Timing
Num
Characteristic
Min
Max
Unit
M9
MII_CRS, MII_COL minimum pulse width
1.5
—
MII_TX_CLK period
MPC885/MPC880 Hardware Specifications, Rev. 3
73
Freescale Semiconductor
FREESCALE [ Freescale ]
