UTOPIA AC Electrical Specifications
2
Figure 69 shows the I C bus timing.
SDA
202
203
204
208
205
207
SCL
206
209
210
211
Figure 69. I2C Bus Timing Diagram
13 UTOPIA AC Electrical Specifications
Table 30, Table 31, and Table 32, show the AC electrical specifications for the UTOPIA interface.
Table 30. UTOPIA Master (Muxed Mode) Electrical Specifications
Num
Signal Characteristic
Direction
Min
Max
Unit
U1
UtpClk rise/fall time (internal clock option)
Output
4 ns
50
ns
%
Duty cycle
Frequency
50
33
MHz
ns
U2
UTPB, SOC, RxEnb, TxEnb, RxAddr, and TxAddr active delay (and
PHREQ and PHSEL active delay in multi-PHY mode)
Output
2 ns
16 ns
U3
U4
UTPB, SOC, Rxclav and Txclav setup time
UTPB, SOC, Rxclav and Txclav hold time
Input
Input
4 ns
1 ns
ns
ns
Table 31. UTOPIA Master (Split Bus Mode) Electrical Specifications
Num
Signal Characteristic
Direction
Min
Max
Unit
U1
UtpClk rise/fall time (Internal clock option)
Output
4 ns
50
ns
%
Duty cycle
Frequency
50
33
MHz
ns
U2
UTPB, SOC, RxEnb, TxEnb, RxAddr and TxAddr active delay
(PHREQ and PHSEL active delay in multi-PHY mode)
Output
2 ns
16 ns
U3
U4
UTPB_Aux, SOC_Aux, Rxclav and Txclav setup time
UTPB_Aux, SOC_Aux, Rxclav and Txclav hold time
Input
Input
4 ns
1 ns
ns
ns
MPC885/MPC880 Hardware Specifications, Rev. 3
69
Freescale Semiconductor
FREESCALE [ Freescale ]
