FEC Electrical Characteristics
Figure 74 shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
M9
Figure 74. MII Async Inputs Timing Diagram
15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 37 provides information on the MII serial management channel signal timing. The FEC functions correctly
with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.
Table 37. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10 MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
0
—
ns
M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay)
M12 MII_MDIO (input) to MII_MDC rising edge setup
M13 MII_MDIO (input) to MII_MDC rising edge hold
M14 MII_MDC pulse width high
—
10
25
—
—
ns
ns
ns
0
40%
40%
60% MII_MDC period
60% MII_MDC period
M15 MII_MDC pulse width low
Figure 75 shows the MII serial management channel timing diagram.
M14
MM15
MII_MDC (output)
M10
MII_MDIO (output)
M11
MII_MDIO (input)
M12
M13
Figure 75. MII Serial Management Channel Timing Diagram
MPC885/MPC880 Hardware Specifications, Rev. 3
74
Freescale Semiconductor
FREESCALE [ Freescale ]
