Mechanical Data and Ordering Information
16.1 Pin Assignments
Figure 76 shows the top-view pinout of the PBGA package. For additional information, see the MPC885
PowerQUICC Family User’s Manual.
NOTE: This is the top view of the device.
W
V
U
T
TRST
TMS
PA10
PB25
PB23
PC11
PA8
PC8
PA5
PB17
PC7
PA13
PB16
PC4
PC13
PB15
PA11
PE21
PE31
PE17
PE24
PE30
PE14
PE15
PD5
PD6
PE28
PD12
PD4
PE27
PA4
PD7
PA3
PE22
PB28
PB22
PA7 PB19
PB31
PE23
PB27
PB14
PC12
TCK
TDO
PB24
TDI
PC10
PB21
PA6 MII1_COL PC6
PD15
PE29
PD14
PE16
PD13
PA0
PD9
PD10
PD11
PA1
PB29
PC15
PA9
VDDL
VDDH
PC9 PB20
PB18 MII1_CRS PC5
VDDL
PD3
PE19 MII1_TXEN PA2
PE25
PE26
R
P
N
M
L
VDDL
VDDL
VDDH
VDDL
GND
PE20
IRQ7
PD8
PC14
PB26
PA14
N/C
A4
PE18
D8
VDDH
VDDH
GND
GND
MII_MDIO PB30
PA12
PA15
A0
IRQ1
D12
D23
D0
GND
A2
A3
A1
A5
IRQ0
D13
D27
D4
VDDL
VDDH
VDDH
D1
D17
D9
VDDH
GND
GND
VDDL
VDDL
A7
A9
A8
A6
D10
D14
D19
D6
D11
D3
D2
K
J
VDDL
GND
A10
A14
A27
A21
A25
A18
A26
BSA2
WE3
A11
A16
A19
A29
A30
A28
A31
BSA1
WE0
A12
A15
A20
A23
A22
TSIZ1
A13
D5
D15
D18
D21
D25
D29
D30
IPA5
A17
D22
D28
D16
D20
D24
D7
H
G
F
VDDH
VDDL
GND
A24
GND
GND
VDDH
VDDL
VDDH
VDDL
TSIZ0
BSA3
WE1
CLKOUT
IPA2
D26
D31
IPA3
VDDH
E
D
C
B
A
VDDL
VDDL
VSSSYN
IPA6
IPA4
BSA0 GPL_AB2 CS6
CS3
CS1
CS0
WR
BI
TA
BR
BG
BB
IRQ6
BURST
IRQ2
IPB1
IPB3
IPB4
ALEB
IPB2
IPB7
AS
MODCK1 EXTAL RSTCONF IPA7
WE2
CS4
CS7
CE2_A
CE1_A
GPL_A5
GPL_A4
IRQ4
ALEA
OP1 BADDR28 TEXP WAIT_B VSSSYN1 IPA1
OP0 BADDR29 HRESET PORESETVDDLSYN IPA0
GPL_A0
TEA
OE
GPL_AB3 CS5
CS2
GPL_B4
BDIP
TS
IRQ3
IPB5
IPB0
IPB6 BADDR30MODCK2 EXTCLK XTAL SRESET WAIT_A
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 76. Pinout of the PBGA Package
MPC885/MPC880 Hardware Specifications, Rev. 3
76
Freescale Semiconductor
FREESCALE [ Freescale ]
