UTOPIA AC Electrical Specifications
Table 32. UTOPIA Slave (Split Bus Mode) Electrical Specifications
Num
Signal Characteristic
Direction
Min
Max
Unit
U1
UtpClk rise/fall time (external clock option)
Duty cycle
Input
4 ns
60
ns
%
40
Frequency
33
MHz
ns
U2
U3
UTPB, SOC, Rxclav and Txclav active delay
Output
Input
2 ns
4 ns
16 ns
UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr setup
time
ns
U4
UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr hold
time
Input
1 ns
ns
Figure 70 shows signal timings during UTOPIA receive operations.
U1
U1
UtpClk
U2
PHREQn
U3
3
U4
4
RxClav
RxEnb
High-Z at MPHY
High-Z at MPHY
U2
2
UTPB
SOC
U3
3
U4
4
Figure 70. UTOPIA Receive Timing
MPC885/MPC880 Hardware Specifications, Rev. 3
70
Freescale Semiconductor
FREESCALE [ Freescale ]
